This application claims the priority of Korean Patent Application No. 10-2005-0009104, filed on Feb. 1, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor test circuit capable of measuring a plurality of internal DC voltages when the semiconductor device is in a packaged state.
2. Description of the Related Art
When a certain section of a circuit to be configured in a semiconductor device or the state of a predetermined DC voltage line used in the semiconductor device is to be tested or inspected, a probe head is made to contact a node or the DC voltage line of a wafer being manufactured to measure the voltage value of the node or the DC voltage line. However, the voltages and currents measured when the devices are in the wafer state do not necessarily match the voltages and currents measured when the devices are in a packaged state. Therefore, measurement of the voltage or current of a predetermined node or a metal line of a semiconductor device when the device is in the packaged state, in which the assembly process of the semiconductor device has been completed, has greater significance.
In order to measure the voltage or current of a node or a DC voltage line when a semiconductor is in a packaged state, package pins connected to the node or the DC voltage line need to be allocated for testing the same. However, the package pins used for testing are useless in performing actual functions during actual operation of a semiconductor device. Therefore, is beneficial to minimize the number package pins that are consumed for testing operations.
In a semiconductor memory device, the voltage level of an internal DC voltage generated using the power voltage input from an external source is an important factor in determining the operating characteristics of the semiconductor memory device. Thus, numerous test circuits are often times installed in a packaged semiconductor to measure the level of the internal DC voltage.
FIG. 1A is a block diagram a conventional semiconductor test circuit for measuring four internal DC voltages V1 through V4 using a single package pin pad PAD. FIG. 1B is a schematic diagram of a circuit that generates control signals CON1, CON2, CON1B, and CON2B used in the semiconductor test circuit illustrated in FIG. 1A.
Referring to FIG. 1A, the semiconductor test circuit is installed in a semiconductor device, and connection relationships of six areas A1 through A6 of the device illustrated with dotted circles are to be monitored during the manufacturing process. For example, when the area A1 and the area A5 are connected, a voltage value of a first electrical signal V1 can be measured using the pad PAD in response to a first control signal CON1 and CON1B. The pad PAD is electrically connected to a package pin, and thus the value of an internal electrical signal V1 of a chip can be monitored when the chip is in a packaged state. However, the conventional semiconductor test circuit illustrated in FIG. 1A cannot select another electrical signal for testing, for example V2, V3, or V4, once the assembly process is completed, because the electrical signal to be tested is determined during the manufacturing process.
In addition, referring to FIG. 1B, a pull-up voltage Vpu applied to gates of transistors M1 and M2 for pulling up a control signal transmits a predetermined stable voltage following a predetermined time period when power is supplied to the semiconductor device. As a result, a delay time is required for proper measurement of the electrical signal, thereby increasing the time required for testing the semiconductor device.